From ab774f10d9166fe608222cd967e2be8e18eb7a07 Mon Sep 17 00:00:00 2001
From: premultiply <4681172+premultiply@users.noreply.github.com>
Date: Sat, 1 Mar 2025 10:35:18 +0100
Subject: [PATCH] Vestel: fix phase register usage (#19277)

---
 charger/vestel.go | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/charger/vestel.go b/charger/vestel.go
index 1066d0cb3..ee8b1599e 100644
--- a/charger/vestel.go
+++ b/charger/vestel.go
@@ -105,7 +105,7 @@ func NewVestel(ctx context.Context, uri string, id uint8) (api.Charger, error) {
 		phasesS func(int) error
 		phasesG func() (int, error)
 	)
-	if b, err := wb.conn.ReadHoldingRegisters(vestelRegNumberPhases, 1); err == nil && binary.BigEndian.Uint16(b) == 1 {
+	if b, err := wb.conn.ReadInputRegisters(vestelRegNumberPhases, 1); err == nil && binary.BigEndian.Uint16(b) == 1 {
 		phasesS = wb.phases1p3p
 		phasesG = wb.getPhases
 	}
@@ -314,6 +314,12 @@ func (wb *Vestel) Diagnose() {
 		fmt.Printf("Firmware:\t%s\n", b)
 	}
 	if b, err := wb.conn.ReadHoldingRegisters(vestelRegFailsafeTimeout, 1); err == nil {
-		fmt.Printf("Failsafe timeout (plain):\t%d\n", binary.BigEndian.Uint16(b))
+		fmt.Printf("Failsafe timeout:\t%#x\n", binary.BigEndian.Uint16(b))
+	}
+	if b, err := wb.conn.ReadInputRegisters(vestelRegNumberPhases, 1); err == nil {
+		fmt.Printf("Number of phases:\t%#x\n", binary.BigEndian.Uint16(b))
+	}
+	if b, err := wb.conn.ReadHoldingRegisters(vestelRegPhasesSwitch, 1); err == nil {
+		fmt.Printf("Phase switch:\t%#x\n", binary.BigEndian.Uint16(b))
 	}
 }